1. Technical Field
The present invention relates generally to computer systems and in particular to a computer system designed as a system on a chip (SoC). Still more particularly, the present invention relates to a method and system for manipulating the issuance of requests from a request FIFO of a SoC when a prior request is retried.
2. Description of the Related Art
The computer industry has made significant developments in integrated circuit (IC) technology in recent years. For example, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. The system-on-a-chip concept refers to a system in which, ideally, all the necessary integrated circuits are fabricated on a single die or substrate. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces (e.g., external bus interface), memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called “cores”.
With a SoC, processed requests are sent from a core referred to as an initiator to a target (which may also be a core). An initiator (or master or busmaster as it is sometimes called) is any device capable of generating a request and placing that request on the bus to be transmitted to a target. Thus, for example, either a processor or DMA controller may be an initiator.
Some initiators, called “caching-initiators”, internally cache copies of the contents stored in the targets. A caching-initiator includes a cache for holding duplicate contents of a target (memory), a request-port for initiating requests and a snoop-port for snooping the contents of the cache when other initiators access the targets.
Targets (or slaves) are the receiving component that receives the initiator-issued requests and responds according to set protocols. A request is sometimes broadcasted to multiple targets, but based on some of the attributes of the request (such as the address), only one target “claims” the request and responds.
In order to complete the connections between initiators and targets, the SoC includes an on-chip bus utilized to connect multiple initiators and targets. The system bus consists of an interface to the caching-initiators and a separate interface to the targets and logic between the interfaces. The logic between the interfaces is called a “bus controller”. This configuration is typical among system-on-a-chip (SoC) buses, where all the initiators, targets and the bus controller are on the same chip (die). In current systems, this bus is referred to as processor local bus (PLB) and has associated logic, PLB Macro. The “PLB Macro” is a block of logic that acts as the bus controller, interconnecting all the devices (i.e., initiators and targets) of the SoC.
A key component of PLB macro utilized to order requests being sent from an initiator to various targets is the request FIFO. Each request sent from the initiator is placed in the request FIFO and then the oldest request in the request FIFO is issued to the arbiter. The arbiter receives a request from each request FIFO and directs the requests to their respective targets.
The Bus Controller consists of a “request queue”, an arbiter, routing logic and miscellaneous buffering and registering logic. The “request queue” is a FIFO that holds a multitude of pending requests from an initiator. Requests are pipelined by the initiators into the “request queue” of the bus controller. This means that a new request is sent by the initiator before any response is received for previous sent requests. The FIFO structure of the request queue (hereinafter referred to as request FIFO) ensures that the transaction ordering intended by the initiator is maintained. This order is simply indicated by the order in which the initiator queues its requests. There is one request FIFO for each initiator. Each request FIFO sends its output (the oldest request) to the arbiter. The arbiter selects which request is “granted” from among the pending requests from each of the request FIFOs. When a request is “granted”, it is broadcast to the snoopers and the targets. The routing logic directs the appropriate signals to/from the initiator associated with the granted request and the appropriate target.
Targets typically acknowledge a request when the request is received, however, if the target is busy for some reason, the target may instead signal “retry” indicating that the current request should be resent. Because of the FIFO structure of the request queue, when a request is granted, but then subsequently retried by the target, the request remains on the “output” of the FIFO. The request is later repeated when the arbiter grants it again, without requiring any activity from the initiator. Notably, with this method of scheduling requests from a FIFO, the next request in the FIFO is forced to wait until the previously granted request is accepted by its target. There is, therefore, a built-in uncertainty regarding when a request within the request FIFO is actually granted. A request may be forced to wait a number of clock cycles while the previously granted request is retried a number of times.
Significant performance degradation exists with current systems for several reasons. For example, the next request may go to a different target that is not busy. Also, the next request has no dependency on the granted request and thus there is not reason why the next request should have to wait until completion of the granted request. Additionally, because there is no guarantee that the target will accept the granted request within a reasonable time period (i.e., the target may be in a busy state for an indefinite period of time), forcing the next request to wait on completion of the granted request may result in a deadlock within the system.
The present invention recognizes that it would be desirable to be able to move forward through the request FIFO, particularly when subsequent requests are not dependent on the prior granted request, which has been retried. A method and system that enables dynamic re-ordering of a granted request relative to subsequent requests within the request FIFO when the granted request is retried would be a welcome improvement. These and other benefits are provided herein.